The present invention relates to a semiconductor device and more particularly to a high-speed bipolar transistor.
As a technique of fabricating a semiconductor integrated circuit composed of bipolar transistors and particularly a high-speed device, a method has been proposed in which emitter/base separation is done in a self-aligned manner and an external base region is formed by diffusion from a base electrode made of polysilicon so that the external base region and an internal base region are formed under an optimum condition, respectively.
FIG. 12 is a sectional view showing one example of a structure of the prior art high-speed bipolar transistor. In FIG. 12, reference numeral 1 denotes a semiconductor substrate (hereinafter referred to simply as "substrate") of P.sup.- type silicon (Si) single crystal; 2 an N.sup.+ collector embedded layer; 3 a P.sup.+ type diffused layer for separation of a lower part; 4 an N.sup.- type epitaxial layer; 5 an N type well region formed in the epitaxial layer 4; and 6 a P type well region formed similarly in the epitaxial layer 4. Reference numeral 7 denotes a field oxide film; 8 a P.sup.+ type diffused layer for element isolation formed in an underlying layer of the field oxide film 7; 9 an N.sup.+ type collector lead out layer; 10 a base electrode of polysilicon; 11 a P.sup.+ type external base region formed by impurity diffusion from the base electrode 10; and 12 a P type internal base region.
Reference numeral 13 denotes an emitter electrode of polysilicon; 14 an N.sup.+ type emitter region formed by impurity diffusion from the emitter electrode 13; 15 a side wall oxide film for insulating the base electrode 10 and the emitter electrode 13 from each other; 16 a thin film formed on the surface of the internal base region 12; 17a, 17b and 17c an oxide film, respectively; 18 an inter-layer insulating film; and 19 electrode wiring layers connected to the base electrode 10, emitter electrode 13 and collector lead out layer 9, respectively.
An explanation will be mainly given of active regions of the bipolar transistor having such a configuration as mentioned above.
FIG. 13 is an enlarged view of region A and the periphery thereof in FIG. 12. As seen from the figure, the base electrode 10 and emitter electrode 13, which are made of polysilicon, constitute such a structure as they are insulated in a self-aligned manner from each other using the side wall oxide film 15 (hereinafter referred to as "self-aligned double polysilicon structure").
The bipolar transistor having such a self-aligned type double poly-silicon structure is fabricated by the following process. After a polysilicon film 10a (not shown) constituting the base electrode 10 is formed so as to abut on silicon in the N type well region 5 which is a part of the epitaxial layer 4, oxide films 17a, 17b and 17c are successively formed. Thereafter, the oxide films 17c and 17b within a zone constituting the internal base region 12 are successively etched away. The thin oxide film 16 is formed, and ions are implanted for forming the internal base region 12. After the side wall oxide film 15 is formed, the emitter electrode 13 is formed.
Thus, when etching is effected to form the internal base region in the polysilicon film 10a constituting the base electrode 10, the N type well region 5 is also over-etched because of a small selection ratio for etching between the polysilicon silicon 10a and the underlying N type region 5 (silicon layer), thereby forming a depression 20. Assuming that the depression 20 has a depth of D, as shown in FIG. 13, the internal base region 12 formed just below the depression 20 has a surface height lower by D than that of the external base region 11 formed outside the depression 20.
In this way, in the conventional bipolar transistor, the N type well region 5 is etched by the process margin when the polysilicon film 10a is etched, thereby forming the depression 20. But, the depth of the depression 20 was not managed specially.
On the other hand, in some proposals as disclosed in e.g. Unexamined Published Japanese Patent Application No. SHO. 60-195968, for the purpose of improving the cut-off frequency f.sub.T (i.e, frequency when the gain is 1) of the bipolar transistor by shortening the distance from the internal base region 12 to the collector embedded layer 2, D which exceeds a certain value was set to form the depression 20 having the corresponding depth.
The end of the internal base region 12 which is the neighborhood of the junction with the external base region 11 refers to a link base portion 21. In the conventional bipolar transistor in which the internal base region 12 is formed at a low position by one step, the link base portion 12 has a shape which is not gently sloping horizontally but round. For this reason, the electric field applied to the base/collector junction when the bipolar transistor operates is apt to concentrate at the link base portion so that the electric field applied to the link base portion 21 increases. When the electric field applied to the link base 21 increases, impact ionizing becomes severe, and the hot carriers thus generated will be stored in the thin oxide film 16 and side wall oxide film 15, or boundary between these films and silicon. Further, when the amount of charges stored increases, the emitter/base junction and base/collector junction will be destroyed.